
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity latch_shifter is
	PORT (
	output : out STD_LOGIC_VECTOR (63 downto 0);
	load_control : in STD_LOGIC; -- to load zeros into higher 32 bits, or to take from adder
	shift_control : in STD_LOGIC;
	adder_in : in STD_LOGIC_VECTOR (31 downto 0);
	adder_carry : in STD_LOGIC;
	clk : in STD_LOGIC;
	disable_changes : in STD_LOGIC
	);
end latch_shifter;

architecture Behavioral of latch_shifter is
	
	signal latch : STD_LOGIC_VECTOR(63 downto 0);
begin
	process (clk)
	begin 
		if (clk'event and clk = '1') then
			
			if (disable_changes = '1') then
			
			elsif (load_control = '1') then --- load in zeros regardless
				latch(63 downto 32) <= "00000000000000000000000000000000";
				latch(31 downto 0) <= "00000000000000000000000000000000";
				
			else				
				--- shift right if need be
				if (shift_control = '1') then
					latch(15 downto 0) <= latch(31 downto 16);
					latch(31 downto 16) <= adder_in(15 downto 0);
					latch(47 downto 32) <= adder_in(31 downto 16);
					latch(63 downto 49) <= "000000000000000";
					latch(48) <= adder_carry;
				else
					latch(63 downto 32) <= adder_in;
				end if;
				
				
			end if;
		end if;
		
		
	end process;
	output <= latch;
end Behavioral;

